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» Model Checking: Back and Forth between Hardware and Software
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MSS
1999
IEEE
150views Hardware» more  MSS 1999»
13 years 9 months ago
Performance Benchmark Results for Automated Tape Library High Retrieval Rate Applications - Digital Check Image Retrievals
Benchmark tests have been designed and conducted for the purpose of evaluating the use of automated tape libraries in on-line digital check image retrieval applications. This type...
John Gniewek, George Davidson, Bowen Caldwell
CODES
2000
IEEE
13 years 9 months ago
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off
This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance require...
Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Stee...
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
13 years 9 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 10 months ago
galsC: A Language for Event-Driven Embedded Systems
— We introduce galsC, a language designed for programming event-driven embedded systems such as sensor networks. galsC implements the TinyGALS programming model. At the local lev...
Elaine Cheong, Jie Liu
CORR
2010
Springer
71views Education» more  CORR 2010»
13 years 4 months ago
Sampled Semantics of Timed Automata
Sampled semantics of timed automata is a nite approximation of their dense time behavior. While the former is closer to the actual software or hardware systems ed granularity of ti...
Parosh Aziz Abdulla, Pavel Krcál, Wang Yi