168 search results - page 1 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
RSP
2003
IEEE
13 years 11 months ago
2003
IEEE
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
LCTRTS
2001
Springer
13 years 10 months ago
2001
Springer
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
ISCAPDCS
2001
13 years 7 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...