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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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DSD
2002
IEEE
96views Hardware» more  DSD 2002»
13 years 10 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
TC
2010
13 years 3 months ago
The Design and Evaluation of a Self-Organizing Superpeer Network
—Superpeer architectures exploit the heterogeneity of nodes in a peer-to-peer (P2P) network by assigning additional responsibilities to higher capacity nodes. In the design of a ...
Pawel Garbacki, Dick H. J. Epema, Maarten van Stee...
IJHPCA
2010
117views more  IJHPCA 2010»
13 years 3 months ago
Fine-Grained Multithreading Support for Hybrid Threaded MPI Programming
As high-end computing systems continue to grow in scale, recent advances in multiand many-core architectures have pushed such growth toward more denser architectures, that is, mor...
Pavan Balaji, Darius Buntinas, David Goodell, Will...
NABIC
2010
13 years 3 days ago
Regional ACO-based routing for load-balancing in NoC systems
Abstract--Ant Colony Optimization (ACO) is a problemsolving technique that was inspired by the related research on the behavior of real-world ant colony. In the domain of Network-o...
Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, An-Ye...
CASES
2008
ACM
13 years 7 months ago
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
Chengmo Yang, Alex Orailoglu