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DATE
2010
IEEE
170views Hardware» more  DATE 2010»
13 years 10 months ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
DAC
2008
ACM
13 years 7 months ago
Technology exploration for graphene nanoribbon FETs
Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics because of their excellent carrier transport properties and potential for large scale proc...
Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik...
MTDT
2003
IEEE
164views Hardware» more  MTDT 2003»
13 years 10 months ago
Applying Defect-Based Test to Embedded Memories in a COT Model
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
Robert C. Aitken
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
13 years 11 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ISQED
2009
IEEE
126views Hardware» more  ISQED 2009»
14 years 7 days ago
Robust differential asynchronous nanoelectronic circuits
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
Bao Liu