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    » Modeling QCA for area minimization in logic synthesis
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    EMNETS
    2007
    176views Sensor Networks» more  EMNETS 2007»
    SeeDTV: deployment-time validation for wireless sensor networks
    13 years 9 months ago
    SeeDTV: deployment-time validation for wireless sensor networks
    Download  www.cs.virginia.edu
    Deployment of a wireless sensor network (WSN) system is a critical step because theoretical models and assumptions often differ from real environmental characteristics and perform...
    H. Liu, Leo Selavo, John A. Stankovic
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    ASE
    2005
    137views more  ASE 2005»
    Rewriting-Based Techniques for Runtime Verification
    13 years 5 months ago
    Rewriting-Based Techniques for Runtime Verification
    Download  www.havelund.com
    Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
    Grigore Rosu, Klaus Havelund
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    DAC
    2009
    ACM
    168views Computer Architecture» more  DAC 2009»
    Analysis and mitigation of process variation impacts on Power-Attack Tolerance
    14 years 6 months ago
    Analysis and mitigation of process variation impacts on Power-Attack Tolerance
    Download  www.rfid-cusp.org
    Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
    Lang Lin, Wayne P. Burleson
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