78 search results - page 2 / 16 » Modeling QCA for area minimization in logic synthesis |
JOLLI
1998
13 years 5 months ago
1998
When reasoning about complex domains, where information available is usually only partial, nonmonotonic reasoning can be an important tool. One of the formalisms introduced in thi...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
FPGA
1995
ACM
13 years 9 months ago
1995
ACM
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height...
GLVLSI
2008
IEEE
14 years 7 days ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we present a new logic synthesis method for PLA with 2-input logic elements. A PLA with 2-input logic elements can achieve low-power dissipation and high-speed oper...