588 search results - page 1 / 118 » Modeling and Verifying Circuits Using Generalized Relative T... |
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
ASYNC
2002
IEEE
13 years 9 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
FMCAD
2008
Springer
13 years 6 months ago
2008
Springer
Abstract--This paper presents the verification of an asynchronous arbiter modeled at the circuit level with non-linear ordinary differential equations. We use Brockett's annul...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
LATA
2010
Springer
14 years 2 months ago
2010
Springer
Timed automata has been used as a powerful formalism for specifying, designing, and analyzing real time systems. We consider the generalization of timed automata to Pushdown Timed ...