Sciweavers

202 search results - page 1 / 41
» Modeling design constraints and biasing in simulation using ...
Sort
View
ICCAD
1999
IEEE
81views Hardware» more  ICCAD 1999»
13 years 9 months ago
Modeling design constraints and biasing in simulation using BDDs
Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulatio...
Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller,...
TACAS
2000
Springer
151views Algorithms» more  TACAS 2000»
13 years 8 months ago
Salsa: Combining Constraint Solvers with BDDs for Automatic Invariant Checking
Salsa is an invariant checker for speci cations in SAL the SCR Abstract Language. To establish a formula as an invariant without any user guidance Salsa carries out an induction pr...
Ramesh Bharadwaj, Steve Sims
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
13 years 6 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
14 years 1 months ago
An analytical model for negative bias temperature instability
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
13 years 10 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...