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PC
2011
318views Management» more  PC 2011»
13 years 17 days ago
High-performance message-passing over generic Ethernet hardware with Open-MX
In the last decade, cluster computing has become the most popular high-performance computing architecture. Although numerous technological innovations have been proposed to improv...
Brice Goglin
HCW
1998
IEEE
13 years 10 months ago
Implementing Distributed Synthetic Forces Simulations in Metacomputing Environments
A distributed, parallel implementation of the widely used Modular Semi-Automated Forces ModSAF Distributed Interactive Simulation DIS is presented, with Scalable Parallel Processo...
Sharon Brunett, Dan Davis, Thomas Gottschalk, Paul...
CODES
2007
IEEE
13 years 12 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
IEEEPACT
2008
IEEE
14 years 1 days ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
13 years 11 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...