188 search results - page 38 / 38 » Modeling of Interconnection Networks in Massively Parallel P... |
CGO
2010
IEEE
14 years 1 days ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
TECS
2008
13 years 5 months ago
2008
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
AINA
2009
IEEE
13 years 12 months ago
2009
IEEE
The architectures which support modern supercomputing machinery are as diverse today, as at any point during the last twenty years. The variety of processor core arrangements, thr...