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» Modeling out-of-order processors for WCET analysis
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BIRTHDAY
2006
Springer
13 years 8 months ago
Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
Steffen Knapp, Wolfgang J. Paul
ESTIMEDIA
2006
Springer
13 years 8 months ago
Loop Nest Splitting for WCET-Optimization and Predictability Improvement
This paper presents the influence of the loop nest splitting source code optimization on the worst-case execution time (WCET). Loop nest splitting minimizes the number of executed...
Heiko Falk, Martin Schwarzer
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
13 years 3 months ago
A proposal for real-time interfaces in SPEEDS
Abstract—The SPEEDS project is aimed at making rich components models (RCM) into a mature framework in all phases of the design of complex distributed embedded systems. The RCM m...
Purandar Bhaduri, Ingo Stierand