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» Modeling transactional memory workload performance
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ICS
2005
Tsinghua U.
13 years 11 months ago
A performance-conserving approach for reducing peak power consumption in server systems
The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing eno...
Wesley M. Felter, Karthick Rajamani, Tom W. Keller...
MICRO
2008
IEEE
114views Hardware» more  MICRO 2008»
14 years 5 days ago
Toward a multicore architecture for real-time ray-tracing
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting intera...
Venkatraman Govindaraju, Peter Djeu, Karthikeyan S...
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
13 years 11 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
HPCA
2008
IEEE
14 years 6 months ago
Automated microprocessor stressmark generation
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, ...
ASPLOS
2006
ACM
13 years 11 months ago
AVIO: detecting atomicity violations via access interleaving invariants
Concurrency bugs are among the most difficult to test and diagnose of all software bugs. The multicore technology trend worsens this problem. Most previous concurrency bug detect...
Shan Lu, Joseph Tucek, Feng Qin, Yuanyuan Zhou