38 search results - page 1 / 8 » Modeling wire delay, area, power, and performance in a simul... |
IBMRD
2006
13 years 9 months ago
2006
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectu...
ICCAD
1994
IEEE
14 years 1 months ago
1994
IEEE
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
14 years 1 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
ICCD
2006
IEEE
14 years 6 months ago
2006
IEEE
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...