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IBMRD
2006

Modeling wire delay, area, power, and performance in a simulation infrastructure

8 years 6 months ago
Modeling wire delay, area, power, and performance in a simulation infrastructure
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectural specification of a processor, Justice estimates the area of each module of the processor and generates a floorplan of the processor. From the floorplan, Justice computes the length and delay of critical communication paths in the architecture. It then modifies the architectural specification by adding delay elements on communication paths whose delay is one or more clock cycles. This modified architectural description is passed back to the Liberty infrastructure, which creates a simulator for the architecture. Justice also estimates the per-access power consumption of each module in an architecture and inserts activity counters to measure how often modules are used. After simulation, a post-processing pass computes the total power consumed by each module and overall power consumption. To illustrate the ca...
Nicholas P. Carter, Azmat Hussain
Added 12 Dec 2010
Updated 12 Dec 2010
Type Journal
Year 2006
Where IBMRD
Authors Nicholas P. Carter, Azmat Hussain
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