Transaction Level Models are widely being used as high-level reference models during embedded systems development. High simulation speed and great modeling flexibility are the ma...
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
Support vector machines (SVMs) have proven to be a powerful technique for pattern classification. SVMs map inputs into a high dimensional space and then separate classes with a hy...
William M. Campbell, Joseph P. Campbell, Douglas A...
The analysis phase constitutes an essential step in the development of information systems. Nevertheless, learning materials design activities currently have reduced the analysis ...
A state/event model is a concurrent version of Mealy machines used for describing embedded reactive systems. This paper introduces a technique that uses compositionality and depend...