25 search results - page 4 / 5 » Multi-Domain Clock Skew Scheduling |
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
DATE
2006
IEEE
13 years 12 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
EDCC
1999
Springer
13 years 10 months ago
1999
Springer
In this paper we present a new fault tolerant clock synchronization algorithm called the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of...