14 search results - page 2 / 3 » Multi-layer parallel decoding algorithm and vlsi architectur... |
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
VTC
2008
IEEE
13 years 11 months ago
2008
IEEE
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
ICASSP
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...