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ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
13 years 11 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
FCCM
2008
IEEE
118views VLSI» more  FCCM 2008»
13 years 11 months ago
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
François Charot, Christophe Wolinski, Nicol...
SIPS
2008
IEEE
13 years 11 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
ICASSP
2008
IEEE
13 years 11 months ago
Implementation of message-passing algorithms for the acquisition of spreading codes
A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative Message Passing (iMP) to be run on loopy...
Massimo Rovini, Fabio Principe, Luca Fanucci, Marc...