79 search results - page 1 / 16 » Multi-level neutrality in optimization |
CEC
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— This paper explores the idea of neutrality in heuristic optimization algorithms. In particular, the effect of having multiple levels of neutrality in representations is...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ICDCS
2008
IEEE
13 years 11 months ago
2008
IEEE
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
EUROGP
2001
Springer
13 years 9 months ago
2001
Springer
This work is a study of neutrality in the context of Evolutionary Computation systems. In particular, we introduce the use of explicit neutrality with an integer string coding sche...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...