126 search results - page 2 / 26 » Multiple FPGA Partitioning with Performance Optimization |
FPGA
2005
ACM
13 years 11 months ago
2005
ACM
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
CODES
2010
IEEE
13 years 2 months ago
2010
IEEE
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
FCCM
2002
IEEE
13 years 10 months ago
2002
IEEE
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...