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IPPS
2003
IEEE
13 years 9 months ago
Multiple Instruction Stream Control for an Associative Model of Parallel Computation
This paper describes a system software design for multiple instruction stream control in a massively parallel associative computing environment. The purpose of providing multiple ...
Michael Scherger, Johnnie W. Baker, Jerry L. Potte...
IPPS
2007
IEEE
13 years 11 months ago
On the Power of the Multiple Associative Computing (MASC) Model Related to That of Reconfigurable Bus-Based Models
: The MASC model is a multi-SIMD model that uses control parallelism to coordinate the interaction of data parallel threads. It supports a generalized associative style of parallel...
Mingxian Jin, Johnnie W. Baker
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ICS
2007
Tsinghua U.
13 years 10 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally
IPPS
2005
IEEE
13 years 10 months ago
Stream PRAM
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
Darrell R. Ulm, Michael Scherger