18 search results - page 2 / 4 » Multiplexer restructuring for FPGA implementation cost reduc... |
FPL
2003
Springer
13 years 10 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
FPL
2011
Springer
12 years 4 months ago
2011
Springer
In this paper two compact hardware structures for the computation of the CLEFIA encryption algorithm are presented. One structure based on the existing state of the art and a nove...
FCCM
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...