61 search results - page 2 / 13 » Multiplications of Floating Point Expansions |
ARVLSI
1995
IEEE
13 years 9 months ago
1995
IEEE
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
ARITH
2007
IEEE
13 years 12 months ago
2007
IEEE
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This p...
ARITH
2007
IEEE
13 years 12 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
ARITH
1999
IEEE
13 years 9 months ago
1999
IEEE
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm i...
ARITH
1993
IEEE
13 years 9 months ago
1993
IEEE