11 search results - page 1 / 3 » Multithreaded Extension to Multicluster VLIW Processors for ... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and...
CAMP
2005
IEEE
13 years 6 months ago
2005
IEEE
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
ISCAPDCS
2001
13 years 6 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
ICMCS
2006
IEEE
13 years 10 months ago
2006
IEEE
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...