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» Nanocompilation for the Cell Matrix Architecture
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TVLSI
2008
133views more  TVLSI 2008»
13 years 5 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
13 years 12 months ago
A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
SPAA
2006
ACM
13 years 11 months ago
Packet-mode emulation of output-queued switches
Most common network protocols (e.g., the Internet Protocol) work with variable size packets, whereas contemporary switches still operate with fixed size cells, which are easier t...
Hagit Attiya, David Hay, Isaac Keslassy
BMCBI
2006
143views more  BMCBI 2006»
13 years 5 months ago
Discovering functional gene expression patterns in the metabolic network of Escherichia coli with wavelets transforms
Background: Microarray technology produces gene expression data on a genomic scale for an endless variety of organisms and conditions. However, this vast amount of information nee...
Rainer König, Gunnar Schramm, Marcus Oswald, ...