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» Network-on-Chip Architecture Exploration Framework
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DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 10 months ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
CAL
2008
13 years 4 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
13 years 10 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
MOBILIGHT
2010
13 years 2 months ago
A Framework for the Design Space Exploration of Software-Defined Radio Applications
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...
Thorsten Jungeblut, Ralf Dreesen, Mario Porrmann, ...
RCC
2002
104views more  RCC 2002»
13 years 4 months ago
Architectural Specification, Exploration and Simulation Through Rewriting-Logic
In recent years Arvind's Group at MIT has shown the usefulness of term rewriting theory for the specification of processor architectures. In their approach processors specifi...
Mauricio Ayala-Rincón, Reiner W. Hartenstei...