Sciweavers

77 search results - page 1 / 16
» Network-on-chip link analysis under power and performance co...
Sort
View
ISCAS
2006
IEEE
110views Hardware» more  ISCAS 2006»
13 years 10 months ago
Network-on-chip link analysis under power and performance constraints
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
Manho Kim, Daewook Kim, Gerald E. Sobelman
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
13 years 9 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...
CASES
2007
ACM
13 years 8 months ago
Performance optimal processor throttling under thermal constraints
We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature co...
Ravishankar Rao, Sarma B. K. Vrudhula
ICASSP
2011
IEEE
12 years 8 months ago
Transmit and receive filters for MISO FBMC systems subjected to power constraints
Build upon the OFDM/OQAM scheme this paper addresses the design of linear transmit and receive filters. Aiming at enhancing the robustness against multipath fading, two novel tec...
Marius Caus, Ana I. Pérez-Neira
UIC
2007
Springer
13 years 10 months ago
Maximizing Network Lifetime Under Reliability Constraints Using a Cross-Layer Design in Dense Wireless Sensor Networks
Abstract. Recent experimental studies have shown that radio links between low-power devices are extremely unreliable. In particular, the instability and unpredictability of low-pow...
Shan Guo Quan, Young Yong Kim