35 search results - page 2 / 7 » New subthreshold concepts in 65nm CMOS technology |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
ICASSP
2011
IEEE
12 years 8 months ago
2011
IEEE
This paper proposes an ultra low energy FFT processor suitable for sensor applications. The processor is based on R4MDC but achieves full utilization of computational elements. It...
TVLSI
2008
13 years 4 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
SOCC
2008
IEEE
13 years 11 months ago
2008
IEEE
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...