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ASPDAC
1999
ACM
100views Hardware» more  ASPDAC 1999»
13 years 9 months ago
Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods
We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimat...
Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwa...
TCAD
1998
127views more  TCAD 1998»
13 years 4 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
WSC
2007
13 years 7 months ago
Ant-based approach for determining the change of measure in importance sampling
Importance Sampling is a potentially powerful variance reduction technique to speed up simulations where the objective depends on the occurrence of rare events. However, it is cru...
Poul E. Heegaard, Werner Sandmann
ECCV
2008
Springer
14 years 6 months ago
A Comparative Analysis of RANSAC Techniques Leading to Adaptive Real-Time Random Sample Consensus
The Random Sample Consensus (RANSAC) algorithm is a popular tool for robust estimation problems in computer vision, primarily due to its ability to tolerate a tremendous fraction o...
Rahul Raguram, Jan-Michael Frahm, Marc Pollefeys
VLSID
2007
IEEE
152views VLSI» more  VLSID 2007»
14 years 5 months ago
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...