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» Noise-tolerant dynamic circuit design
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ICCAD
2007
IEEE
281views Hardware» more  ICCAD 2007»
14 years 3 months ago
Archer: a history-driven global routing algorithm
Global routing is an important step in the physical design process. In this paper, we propose a new global routing algorithm Archer, which resolves some of the most common problem...
Muhammet Mustafa Ozdal, Martin D. F. Wong
CODES
2005
IEEE
13 years 11 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
ASPLOS
2008
ACM
13 years 8 months ago
Adapting to intermittent faults in multicore systems
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
GECCO
2009
Springer
130views Optimization» more  GECCO 2009»
14 years 21 days ago
Liposome logic
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
James Smaldon, Natalio Krasnogor, Alexander Camero...
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 3 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert