18 search results - page 4 / 4 » Non-fractional parallelism in LDPC decoder implementations |
ICASSP
2008
IEEE
14 years 7 days ago
2008
IEEE
A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative Message Passing (iMP) to be run on loopy...
FCCM
2004
IEEE
13 years 9 months ago
2004
IEEE
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
FCCM
2003
IEEE
13 years 11 months ago
2003
IEEE
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...