36 search results - page 6 / 8 » OBIG: the Architecture of an Output Buffered Switch with Inp... |
NOCS
2009
IEEE
14 years 14 days ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...
ISCC
2009
IEEE
14 years 14 days ago
2009
IEEE
Abstract—This paper presents a novel scalable switching architecture for input queued switches with its proper arbitration algorithms. In contrast to traditional switching archit...
SIGMETRICS
1990
ACM
13 years 9 months ago
1990
ACM
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
ASMTA
2010
Springer
13 years 3 months ago
2010
Springer
Due to the overall growing demand on the network resources and tight restrictions on the power consumption, the requirements to the long-term scalability, cost and performance capa...
TON
2010
13 years 13 days ago
2010
Abstract--A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unl...