20 search results - page 1 / 4 » OS-aware tuning: improving instruction cache energy efficien... |
IPCCC
2006
IEEE
13 years 11 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
CODES
2005
IEEE
13 years 7 months ago
2005
IEEE
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
CASES
2008
ACM
13 years 7 months ago
2008
ACM
Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Mac...
ISVLSI
2008
IEEE
13 years 12 months ago
2008
IEEE
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...