14 search results - page 3 / 3 » Off-Line Testing of Delay Faults in NoC Interconnects |
ET
2002
13 years 4 months ago
2002
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
CNSR
2010
IEEE
13 years 8 months ago
2010
IEEE
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
TVLSI
2002
13 years 4 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...
VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has se...