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2002

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Using At-Speed BIST to Test LVDS Serializer/Deserializer Function

13 years 4 months ago

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LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...

Magnus Eckersand, Fredrik Franzon, Ken Filliter

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Id	Views	Title	Status

1	122	Using At-Speed BIST to Test LVDS Serializer/Deserializer Function	claim
2	115	CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing	claim
3	111	Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST	claim
4	108	Diagnosis Strategies for Hardware or Software Systems	claim
5	105	An Integrated Framework for the Design and Optimization of SOC Test Solutions	claim
6	97	Test Generation for Crosstalk-Induced Faults: Framework and Computational Results	claim
7	90	Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip	claim
8	85	Signal Integrity: Fault Modeling and Testing in High-Speed SoCs	claim
9	84	Hardware Generation of Random Single Input Change Test Sequences	claim
10	77	Reusing Scan Chains for Test Pattern Decompression	claim
11	72	Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor	claim
12	67	On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST	claim
13	64	Structural Fault Based Specification Reduction for Testing Analog Circuits	claim
14	50	TA-PSV - Timing Analysis for Partially Specified Vectors	claim

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