The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...