10 search results - page 1 / 2 » On Nominal Delay Minimization in LUT-based FPGA Technology M... |
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
FPGA
1995
ACM
13 years 8 months ago
1995
ACM
We study the nominal delay minimization problem in LUTbased FPGA technologymapping, where interconnect delay is assumed proportionalto net fanout size. We prove that the delay-opt...
FPGA
2000
ACM
13 years 8 months ago
2000
ACM
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
DAC
1993
ACM
13 years 9 months ago
1993
ACM
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation o...