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» On Removing Multiple Redundancies in Combinational Circuits
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DATE
2005
IEEE
122views Hardware» more  DATE 2005»
13 years 11 months ago
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
Raja K. K. R. Sandireddy, Vishwani D. Agrawal
ISQED
2009
IEEE
126views Hardware» more  ISQED 2009»
14 years 4 days ago
Robust differential asynchronous nanoelectronic circuits
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
Bao Liu
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
13 years 9 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ECCV
2008
Springer
14 years 7 months ago
Using Multiple Hypotheses to Improve Depth-Maps for Multi-View Stereo
We propose an algorithm to improve the quality of depth-maps used for Multi-View Stereo (MVS). Many existing MVS techniques make use of a two stage approach which estimates depth-m...
Carlos Hernández, George Vogiatzis, Neill D...
ADC
2007
Springer
108views Database» more  ADC 2007»
13 years 11 months ago
Distributed Text Retrieval From Overlapping Collections
In standard text retrieval systems, the documents are gathered and indexed on a single server. In distributed information retrieval (DIR), the documents are held in multiple colle...
Milad Shokouhi, Justin Zobel, Yaniv Bernstein