Sciweavers

82 search results - page 3 / 17
» On Structural vs. Functional Testing for Delay Faults
Sort
View
IOLTS
2000
IEEE
84views Hardware» more  IOLTS 2000»
13 years 10 months ago
Self-Testing of FPGA Delay Faults in the System Environment
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
Andrzej Krasniewski
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
13 years 10 months ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
TODAES
1998
64views more  TODAES 1998»
13 years 5 months ago
Functional test generation for delay faults in combinational circuits
Irith Pomeranz, Sudhakar M. Reddy
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
13 years 11 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...