VTS 2003 - PDF Preprint Papers

VTS 2003 IEEE VLSI Test Symposium

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VTS
2003
IEEE

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Efficient Implication - Based Untestable Bridge Fault Identifier

13 years 10 months ago

Download computing.ece.vt.edu

: This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation [1] is first p...

Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, ...

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Id	Views	Title	Status

1	131	Efficient Implication - Based Untestable Bridge Fault Identifier	claim
2	127	Bist Reseeding with very few Seeds	claim
3	122	A Reconfigurable Shared Scan-in Architecture	claim
4	119	Test Data Compression Using Dictionaries with Fixed-Length Indices	claim
5	119	A Circuit Level Fault Model for Resistive Opens and Bridges	claim
6	115	Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs	claim
7	115	Fault Testing for Reversible Circuits	claim
8	104	Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns	claim
9	95	Built-In Reseeding for Serial Bist	claim
10	95	Testing SoC Interconnects for Signal Integrity Using Boundary Scan	claim
11	89	Detecting Intra-Word Faults in Word-Oriented Memories	claim
12	89	Diagnosis of Delay Defects Using Statistical Timing Models	claim
13	88	Use of Multiple IDDQ Test Metrics for Outlier Identification	claim
14	87	An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits	claim
15	87	Efficient Seed Utilization for Reseeding based Compression	claim
16	83	SOC Test Scheduling Using Simulated Annealing	claim
17	81	Test Resource Partitioning and Optimization for SOC Designs	claim
18	69	Keynote Address	claim
19	55	Deterministic Test Vector Decompression in Software Using Linear Operations	claim

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