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ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
13 years 11 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
14 years 1 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
TON
2012
11 years 7 months ago
A Transport Protocol to Exploit Multipath Diversity in Wireless Networks
Abstract—Wireless networks (including wireless mesh networks) provide opportunities for using multiple paths. Multihoming of hosts, possibly using different technologies and prov...
Vicky Sharma, Koushik Kar, K. K. Ramakrishnan, Shi...
TELSYS
2002
128views more  TELSYS 2002»
13 years 4 months ago
An Evaluation of Shared Multicast Trees with Multiple Cores
Native multicast routing protocols have been built and deployed using two basic types of trees: singlesource, shortest-path trees and shared, core-based trees. Core-based multicas...
Daniel Zappala, Aaron Fabbri, Virginia Mary Lo
EMSOFT
2005
Springer
13 years 10 months ago
Compiler-guided register reliability improvement against soft errors
With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely ...
Jun Yan, Wei Zhang