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» On Timing Analysis of Combinational Circuits
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ICCAD
1999
IEEE
75views Hardware» more  ICCAD 1999»
13 years 10 months ago
Functional timing optimization
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimi...
Alexander Saldanha
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 29 days ago
On hierarchical statistical static timing analysis
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneid...
DATE
2008
IEEE
92views Hardware» more  DATE 2008»
14 years 20 days ago
Latch Modeling for Statistical Timing Analysis
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...
Sean X. Shi, Anand Ramalingam, Daifeng Wang, David...
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 3 months ago
A unified non-rectangular device and circuit simulation model for timing and power
— For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit char...
Sean X. Shi, Peng Yu, David Z. Pan
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
13 years 11 months ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...