1529 search results - page 3 / 306 » On Timing Analysis of Combinational Circuits |
ICCAD
1999
IEEE
13 years 10 months ago
1999
IEEE
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimi...
DATE
2009
IEEE
14 years 29 days ago
2009
IEEE
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
DATE
2008
IEEE
14 years 20 days ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
— For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit char...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...