4 search results - page 1 / 1 » On error modeling of electrical bugs for post-silicon timing... |
ASPDAC
2012
ACM
12 years 17 days ago
2012
ACM
—There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timi...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Verification remains an integral and crucial phase of today’s microprocessor design and manufacturing process. Unfortunately, with soaring design complexities and decreasing...
HICSS
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper develops a model of an electrical power system, with its inherent embedded communication system, for the purpose of studying the characteristics of power system measure...
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...