100 search results - page 4 / 20 » On hierarchical statistical static timing analysis |
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
DATE
2008
IEEE
14 years 11 days ago
2008
IEEE
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
GLVLSI
2008
IEEE
14 years 11 days ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...