7 search results - page 1 / 2 » On path-based learning and its applications in delay test an... |
DAC
2004
ACM
14 years 5 months ago
2004
ACM
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ITNG
2010
IEEE
13 years 9 months ago
2010
IEEE
—This paper presents the design of BAUT, a tutoring system that explores statistical approach for providing instant project failure analysis. Driven by a Bayesian Network (BN) in...
PAM
2010
Springer
13 years 11 months ago
2010
Springer
The ability to pinpoint the geographic location of IP hosts is compelling for applications such as on-line advertising and network attack diagnosis. While prior methods can accurat...
SASO
2009
IEEE
13 years 11 months ago
2009
IEEE
—In sufficiently large heterogeneous overlays message loss and delays are likely to occur. This has a significant impact on overlay routing, especially on longer paths. The exi...