37 search results - page 7 / 8 » On power and fault-tolerance optimization in FPGA physical s... |
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
ISQED
2007
IEEE
13 years 12 months ago
2007
IEEE
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...