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20
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On process-algebraic verification of asynchronous circuits
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ASYNC
1999
IEEE
110
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Hardware
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ASYNC 1999
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Verification of Delayed-Reset Domino Circuits Using ATACS
13 years 9 months ago
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www.async.ece.utah.edu
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
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ASYNC
2007
IEEE
161
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Hardware
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ASYNC 2007
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Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
13 years 11 months ago
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conferences.computer.org
Mark B. Josephs
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PRDC
2002
IEEE
97
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Applied Computing
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PRDC 2002
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Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method
13 years 9 months ago
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www.async.ece.utah.edu
Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric ...
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CAV
1995
Springer
95
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CAV 1995
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Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings
13 years 8 months ago
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www.cadence.com
Kenneth L. McMillan
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14
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AC
2002
Springer
94
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Software Engineering
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AC 2002
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Timed Verification of Asynchronous Circuits
13 years 4 months ago
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www.configit.com
Jesper B. Møller, Henrik Hulgaard, Henrik R...
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