66 search results - page 1 / 14 » On reducing misspeculations in a pipelined scheduler |
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
HPCA
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...
7
Voted
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Composable multicore systems merge multiple independent cores for running sequential single-threaded workloads. The performance scalability of these systems, however, is limited d...