115 search results - page 21 / 23 » On the Design and Implementation of a Cache-Aware Multicore ... |
IEEEPACT
2008
IEEE
13 years 11 months ago
2008
IEEE
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
SIGARCH
2008
13 years 5 months ago
2008
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
CASES
2009
ACM
13 years 12 months ago
2009
ACM
A common problem in event-triggered real-time systems is caused by low-priority tasks that are implemented as interrupt handlers interrupting and disturbing high-priority tasks th...
RTAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Large-scale storage systems often hold data for multiple applications and users. A problem in such systems is isolating applications and users from each other to prevent their wor...