155 search results - page 2 / 31 » On the Expressive Power of Deep Architectures |
ASPLOS
2012
ACM
12 years 20 days ago
2012
ACM
Numerous data center services exhibit low average utilization leading to poor energy efficiency. Although CPU voltage and frequency scaling historically has been an effective mea...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...